1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having memory cells each of which comprises a volatile memory unit and a nonvolatile memory unit. This invention also relates to a semiconductor memory device having an improved precharge circuit.
2. Description of the Prior Art
Some kinds of semiconductor memories have memory cells each of which comprises a combination of a dynamic random access memory (DRAM) unit and an electrically erasable programmable read-only memory (EEPROM) unit. These memory cells are arranged on a chip to form a memory array. When data is read out of or written into the memory cell (read operation or write operation), only the DRAM unit is operated. On the other hand, both the DRAM unit and EEPROM unit are operated when data stored in the DRAM unit is transferred to the EEPROM unit (store operation) or when data stored in the EEPROM unit is recalled to the DRAM unit (recall operation). Once the data stored in the DRAM unit has been transferred to the EEPROM unit, the data is retained in the EEPROM unit even after power is turned off. This allows the data retained in the EEPROM unit to be recalled to the DRAM unit when the power is turned on again.
As means for respectively performing the read/write, recall, and store operations, it is known to use a read/write timing circuit, a recall timing circuit, and a store timing circuit. Such timing circuits were proposed in "CMOS VLSI Design" published by Baifukan, Japanese Patent Application No. 2-43391, and Nikkei Electronics 1987 (No.418) p.p.167-184. FIG. 11 illustrates one example of a prior art semiconductor memory device in which these timing circuits are used.
In the memory device of FIG. 11, four input signals, i.e., a chip enable signal CE, a nonvolatile enable signal NE, an output enable signal OE, and a write enable signal WE are input from an external circuit to a read/write timing circuit 104, recall timing circuit 105 and store timing circuit 106. These signals are all active low and inactive high logic signals. The chip enable signal CE indicates that the chip on which a memory array 100 is formed is selected, and the nonvolatile enable signal NE is issued to enable the recall or store operation. The output enable signal OE enables data read operation to output data from the memory array to an external device, while the write enable signal WE is used to enable data write operation to input data from an external device to the memory array.
The operation of the memory device of FIG. 11 will be described with reference to FIGS. 12A-12E. When the read operation is to be performed, the chip enable signal CE and output enable signal OE are set LOW to activate the read/write timing circuit 104, while holding the nonvolatile enable signal NE HIGH to disable the recall timing circuit 105 and the store timing circuit 106 (FIG. 12A). In the read operation, the write enable signal WE is held HIGH. When the writing operation is to be performed, the chip enable signal CE and the write enable signal WE are set LOW to activate the read/write timing circuit 104, while holding the nonvolatile enable signal NE and output enable signal OE HIGH (FIG. 12B) (while disabling the recall timing circuit 105 and the store timing circuit 106). The recall operation is performed, as shown in FIG. 12C, by first setting the nonvolatile enable signal NE to LOW to disable the operation of the read/write timing circuit 104 and then setting the output enable signal OE and chip enable signal CE to LOW to enable the recall timing circuit 105. In the recall operation, the write enable signal WE is held HIGH. The store operation is performed, as shown in FIG. 12D, by first setting the nonvolatile enable signal NE to LOW to disable the read/write timing circuit 104 and then setting the write enable signal WE and chip enable signal CE to LOW to enable the store timing circuit 106. In the store operation, the output enable signal OE is held HIGH.
In the DRAM unit, charges gradually leak, and therefore the refresh operation must be carried out to prevent stored data from disappearing. When the refresh operation is to be performed, the output enable signal OE and chip enable signal CE are set LOW to enable the read/write timing circuit 104, while holding the nonvolatile enable signal NE and write enable signal WE HIGH (FIG. 12E) (while disabling the recall timing circuit 105 and the store timing circuit 106). The refresh operation immediately after the store operation may be substituted with the recall operation.
In the semiconductor memory device of FIG. 11, the DRAM units are not provided with a signal amplification function, and therefore the signal output from each DRAM unit must be amplified on the bit line by a sense amplifier. This necessitates the recall operation to be performed for every page, i.e., for every group of memory cells connected to a word line which is addressed by an address counter 108 (which is updated by a timer 107 as shown in FIG. 11 or the rising edge of OE in FIG. 12C). As a result, recalling all pages requires the input operation to be performed the number of times equal to the total number of word lines (for example, 512 times) using the timing shown in FIG. 12C. Thus, in the conventional device in which the timing circuits 104, 105 and 106 are simply combined, there occurs the problem that the timing of inputting external signals is complicated.
FIGS. 15 and 16 illustrate a main amplifying circuit 200 and precharge circuit 300 used in a prior art semiconductor memory device, respectively. The main amplifying circuit 200 comprises a main amplifier 60, and a connection circuit 70. The main amplifier 60 amplifies the signal on a pair of data lines D and D, and outputs the amplified signal onto an output line 56. The connection circuit 70 receives the amplified signal through an inverter 66, and transfers it onto a common data line 57. The data lines D and D are connected to a memory cell via bit lines (not shown). The common data line 57 is connected to an I/O buffer circuit of the semiconductor memory device, and functions as a path for transferring data when data is read from or written into the memory cell. The precharge circuit 300 comprises an N-transistor 81 which is connected between a power source (V.sub.cc) and the common data line 57.
When the read operation is to be performed, a main amplifier enable signal .phi..sub.c and a precharge signal .phi..sub.e are previously set LOW and HIGH, respectively (as shown in FIG. 17). The output line 56 and common data line 57 are biased (or precharged) through a P-transistor 65 and the N-transistor 81, respectively. A P-transistor 64 in the main amplifier 60 is turned on so that the junction point J.sub.a between a pullup P-transistor 61a and a pulldown N-transistor 62a and the junction point J.sub.b between a pullup P-transistor 61b and a pulldown N-transistor 62b are biased to the same potential (V.sub.cc). In the read operation, a write signal .phi..sub.d is maintained HIGH. Thereafter, the precharge signal .phi..sub.e is set LOW to turn off the N-transistor 81, thereby completing the precharge of the common data line 57. The main amplifier enable signal .phi..sub.c is then set HIGH so that the P-transistor 65 is turned off to complete the precharge of the output line 56. At the same time, the P-transistor 64 is turned off, and an N-transistor 63 in the main amplifier 60 is turned on. This enables the combination of the pullup P-transistors 61a and 61b and pulldown N-transistors 62a and 62b to amplify the data signal on the data lines D and D. The amplified data signal is output through the output line 56.
When the main amplifier enable signal .phi..sub.c is set HIGH, the output of a NAND gate 73 in the connection circuit 70 becomes LOW to turn on a P-transistor 72 and turn off an N-transistor 71, the gate of which is connected to the output of NAND gate 73 through an inverter 74. Therefore, the output of the main amplifier 60 on the output line 56 is transferred to the common data line 57 via the inverter 66 and transistors 71 and 72. In this way, the data read operation is performed.
Along with the remarkable progress of memory capacity, the chip size of a semiconductor memory device has gradually increased. As a result, the length of the common data line 57 in a large capacity memory device becomes longer to a degree that the delay time caused by the common data line 57 cannot be neglected. In the semiconductor memory device described above, particularly, the output level of the main amplifier 60 must change by a degree up to as much as the half of the power source potential (V.sub.cc) until it reaches the threshold level of the next stage, resulting in that the delay time caused by the common data line 57 is prolonged.